1. Field of the Invention
The present invention generally relates to the field of electronic waveform sampling circuits, and more specifically to a sample and hold circuit which compensates for signal modulation by resistive current sources and output slew currents using bipolar transistors of a single conductivity type.
2. Description of the Related Art
Sample and hold circuits charge a holding element, which is usually a capacitor, to the instantaneous amplitude of an analog input signal during a tracking or sampling interval, and then uncouple the signal from the capacitor during a holding interval. The sampled voltage which is held by the capacitor is typically applied to an analog-to-digital converter which produces a corresponding digital value which is stored in a random access memory of a waveform processing unit. A set of stored digital values obtained at increments of a sampled waveform constitutes a digital approximation of the analog signal, and can be analyzed or processed using a variety of known algorithms in accordance with a particular application.
FIG. 1 illustrates a basic prior art class A sample and hold circuit 10 including a switchable diode bridge 12 such as described in U.S. Pat. No. 4,659,945, entitled "SAMPLING BRIDGE", issued Apr. 21, 1987 to A. Metz. The bridge 12 has a first bias current node N1 and a second bias current node N2. The anodes of diodes D1 and D3 are connected to the node N2, whereas the cathodes of diodes D2 and D4 are connected to the node N1. The cathodes of the diodes D1 and D3 are connected to the anodes of the diodes D2 and D4 respectively. An analog input voltage signal Vin which is to be sampled is applied to the junction of the diodes D1 and D2 which constitutes an input 14. An output signal Vout appears at the junction of the diodes D3 and D4, which constitutes an output 16, and is applied to a holding circuit 18 including a charging resistor RH and an integrating or holding capacitor CH. A junction 20 is defined between the resistor RH and capacitor CH.
The diode bridge 12 further includes a diode D5 having a cathode connected to the node N2, and a diode D6 having an anode connected to the node N1. The anode of the diode D5 is connected to the cathode of the diode D6. A unity-gain replica of the output signal Vout is fed back through a buffer amplifier A1 to the junction of the diodes D5 and D6 and designated as a bootstrap bias voltage VBS. The diodes D5 and D6 are connected in anti-parallel relation to the diodes D1, D2, D3 and D4.
An NPN bipolar sampling transistor Q2 has a collector connected to the node N1 and an emitter connected to a constant current drain S1. A signal Vsample for selecting or commanding a tracking or sampling mode of operation is applied to the base of the transistor Q2. An NPN bipolar holding transistor Q1 has a collector connected to the node N2 and an emitter connected to the drain S1. A signal Vhold for selecting or commanding a holding mode of operation is applied to the base of the transistor Q1. The drain S1 causes a predetermined constant bias current IBIAS to flow out of the bridge 12 through the node N1 or N2 and whichever transistor Q1 or Q2 is turned on into a voltage source VEE.
A first current source resistor R1 is connected between a voltage source VCC, which produces a voltage higher than the voltage VEE, and the node N2. Diodes D7 and D9 have anodes connected through a second current source resistor R2 to the voltage source VCC and cathodes connected to the anodes of diodes D8 and D10 respectively. The cathodes of the diodes D8 and D10 are connected to the node N1.
The diodes D7, D8, D9 and D10 are connected in the same configuration as the diodes D1, D2, D3 and D4 respectively and enable the resistor R2 to have the same resistance as the resistor R1 and be connected to the same voltage source VCC. Although not specifically illustrated, it is within the scope of the invention to connect the resistors R1 and R2 to different voltage sources.
The circuit 10 is operated in sampling mode by applying the sampling signal Vsample to the transistor Q2 and removing the holding signal Vhold from the transistor Q1. The transistor Q2 is turned on, thereby connecting the node N1 to the drain S1, whereas the transistor Q1 is turned off, thereby disconnecting the node N2 from the drain S1. The diodes D1, D2, D3 and D4 are forward biased, thereby coupling the signal Vin therethrough to the capacitor CH which charges through the resistor RH to the instantaneous value of the signal Vin to produce the signal Vout. The diodes D5 and D6 are reverse biased, and do not pass signal or bias current therethrough.
The bias current IBIAS flows out of the circuit 10 through the drain S1. Under theoretically ideal conditions, half of this current, IBIAS/2, flows through the resistor R1, node N2, diodes D1, D2, D3 and D4, node N1 and transistor Q2 to the drain S1 to forward bias the diodes D1, D2, D3 and D4 and couple the signal Vin to the capacitor CH. Another half IBIAS/2 of the bias current IBIAS flows through the resistor R2, diodes D7, D8, D9 and D10, node N1 and transistor Q2 to the drain S1.
The circuit 10 is operated in holding mode by applying the holding signal Vhold to the transistor Q1 and removing the sampling signal Vsample from the transistor Q2. The transistor Q1 is turned on, thereby connecting the node N2 to the drain S1, whereas the transistor Q2 is turned off, thereby disconnecting the node N1 from the drain S1. The diodes D5 and D6 are forward biased by the bootstrap bias voltage Vbs, thereby causing the diodes D1, D2, D3 and D4 to be reverse biased and not pass signal or bias current therethrough, such that the signal Vin is uncoupled from the capacitor CH.
The current IBIAS flows out of the circuit 10 through the drain S1 in holding mode as it does in sampling mode. Half of this current, IBIAS/2, flows through the resistor R2, diodes D7, D8, D9 and D10, node N1, diodes D5, and D6, node N2 and transistor Q1 to the drain S1 to forward bias the diodes D5 and D6, reverse bias the diodes D1, D2, D3 and D4 and thereby uncouple the signal Vin from the capacitor CH. Another half of this current, IBIAS/2, flows through the resistor R1, node N2 and transistor Q1 to the drain S1.
The diodes D5 and D6 must have a forward voltage drop which is larger than the forward voltage drop of the diodes D1, D2, D3 and D4 in order to cause the diodes D1, D2, D3 and D4 to be reverse biased when the diodes D5 and D6 are forward biased. Where a particular application must be implemented by diodes of a single type, the required effect can be produced by substituting two or more series diodes for each of the diodes D5 and D6, although not specifically illustrated.
Sample and hold circuits are often required to operate at very high speeds. Complementary bipolar integrated circuit fabrication techniques which enable transistors of both NPN and PNP conductivity types to be formed are currently limited in that the circuits produced by these techniques are only capable of operation at low speeds. For this reason, prior art high speed sample and hold circuits such as illustrated in FIG. include only resistors and bipolar devices of a single conductivity type, usually NPN, and are vulnerable to tracking errors caused by non-linear signal modulation.
As described above, under theoretically ideal conditions, bias currents, each having a value of IBIAS/2, flow into the bridge 12 through the resistors R1 and R2 and the nodes N2 and N1 respectively in sampling mode. Under real conditions, however, these bias currents vary in accordance with the magnitude of the signal Vin and produce non-linear errors in the output signal Vout. This effect is known as "resistive current source modulation".
A second source of tracking non-linearity results from the fact that the holding circuit 18 has finite impedance. The resistance of the resistor RH and the capacitance of the capacitor CH determine the noise bandwidth in a class A sample and hold circuit. The holding circuit 18 constitutes a load impedance which must be driven by the bridge 12 over the entire frequency range of the signal Vin. In driving the load impedance, the bridge 12 must source and sink different drive currents into the capacitor CH through the resistor RH and junction 20 which are slew rate (rate of change of the signal Vin) dependent. This drive or slew current also modulates the output signal Vout, and the effect is known as "output slew current modulation".
These two sources of signal modulation have limited the speed, linearity and resolution of class A sample and hold circuits and restricted their use to relatively low performance applications.